From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study - researchr publication authors

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Ney Laert Vilar Calazans, Edson I. Moreno, Fabiano Hessel, Vitor M. da Rosa, Fernando Moraes, Everton Carara. From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study. In Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2003, Sao Paulo, Brazil, September 8-11, 2003. pages 355, IEEE Computer Society, 2003. [doi]

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