Abstract is missing.
- SystemC: From Language to Applications, from Tools to MethodologiesGrant Martin. 3 [doi]
- System-Level Design for FPGAsPatrick Lysaght. 4 [doi]
- High-Performance RF/Microwave Integrated Circuits in Advanced Logic CMOS Technology: The Coming of Age for RF/Digital Mixed-Signal System-on-a-PackageLuiz Franca-Neto. 5 [doi]
- Design of a Low Noise Amplifier for CDMA Transceivers at 900MHz in CMOS 0.35 µmJulio Arlindo Pinto Azevedo, Tales Cleber Pimenta. 9-13 [doi]
- A Methodology for CMOS Low Noise Ampli.er DesignElkim Roa, Joao Navarro Soares, Wilhelmus A. M. Van Noije. 14-19 [doi]
- Design of a Reusable Rail-to-Rail Operational AmplifierPablo Aguirre, Fernando Silveira. 20-25 [doi]
- Design of Operational Transconductance Amplifiers with Improved Gain by Using Graded-Channel SOI nMOSFETsSalvador Pinillos Gimenez, Marcelo Antonio Pavanello, João Antonio Martino, S. Adriaensen, Denis Flandre. 26 [doi]
- Boolean Technology Mapping Based on Logic DecompositionMaurizio Damiani, Andrei Y. Selchenko. 35-40 [doi]
- Retiming Finite State Machines to Control Hardened Data-PathsIvan Augé, François Donnet, Frédéric Pétrot. 41-46 [doi]
- Combining Retiming and Recycling to Optimize the Performance of Synchronous CircuitsLuca P. Carloni, Alberto L. Sangiovanni-Vincentelli. 47-52 [doi]
- Simplification of Toffoli Networks via TemplatesDmitri Maslov, Gerhard W. Dueck, D. Michael Miller. 53 [doi]
- SystemC and the Future of Design Languages: Opportunities for Users and ResearchGrant Martin. 61 [doi]
- A New Pipelined Array Architecture for Signed MultiplicationEduardo A. C. da Costa, Sergio Bampi, José C. Monteiro. 65-70 [doi]
- Novel Design Methodology for High-Performance XOR-XNOR Circuit DesignSumeer Goel, Mohamed A. Elgamel, Magdy A. Bayoumi. 71 [doi]
- Towards a High-Level Synthesis of Reconfigurable Bit-Serial ArchitecturesAchim Rettberg, Florian Dittmann, Mauro Cesar Zanella, Thomas Lehmann. 79-84 [doi]
- DALI: A Methodology for the Co-Design of Dataflow Applications on Hardware/Software ArchitecturesMário P. Véstias, Horácio C. Neto. 85 [doi]
- ME64 - A Highly Scalable Hardware Parallel Architecture Motion Estimation in FPGADiogo Zandonai, Sergio Bampi, Marcel Bergerman. 93-98 [doi]
- Hyperspectral Images Clustering on Reconfigurable Hardware Using the K-Means AlgorithmAbel Guilhermino S. Filho, Alejandro César Frery, Cristiano C. de Araujo, Haglay Alice, Jorge Cerqueira, Juliana A. Loureiro, Manoel Eusebio de Lima, Maria das Gracas S. Oliveira, Michelle Matos Horta. 99-104 [doi]
- Design and Prototyping of Direct Torque Control of Induction Motors in FPGAsSandro Ferreira, Felipe Haffner, Luis Fernando Pereira, Fernando Moraes. 105-110 [doi]
- FPGA-Based Hardware Architecture for Neural Networks: Binary Radix vs. StochasticNadia Nedjah, Luiza de Macedo Mourelle. 111 [doi]
- An XML Format Based Integration Infrastructure for IP Based DesignMarkus Visarius, Johannes Lessmann, Wolfram Hardt, Frank Kelso, Wolfgang Thronicke. 119-124 [doi]
- Tangram - Virtual Integration of Heterogeneous IP Components in a Distributed Co-Simulation EnvironmentUilian Rafael Feijo Souza, Josue Klafke Sperb, Braulio Adriano de Mello, Flávio Rech Wagner. 125-130 [doi]
- A Fast IP-Core Integration Methodology for SoC DesignJulio A. de Oliveira Filho, Manoel Eusebio de Lima, Paulo Romero Martins Maciel, Juliana Moura, Bruno Celso. 131-136 [doi]
- A Universal High-Performance Analog Interface for Signal Processing SOCsEric E. Fabris, Luigi Carro, Sergio Bampi. 137 [doi]
- Architecture and Implementation of Multi-Processor SoCs for Advanced Set-Top Box and Digital TV SystemsSantanu Dutta. 145 [doi]
- Automatic Generation of 1-of-M QDI Asynchronous AddersJoão Leonardo Fragoso, Gilles Sicard, Marc Renaudin. 149-154 [doi]
- Exclusion Relation of k Out of n and the Synthesis of Speed-Independent CircuitsArtur Pereira, Antonio Rui Borges, Antonio Ferrari. 155 [doi]
- Algorithms and Tools for Network on Chip Based System DesignTang Lei, Shashi Kumar. 163-168 [doi]
- SoCIN: A Parametric and Scalable Network-on-ChipCesar Albenes Zeferino, Altamiro Amadeu Susin. 169 [doi]
- A Low Ripple Fully Integrated Charge Pump RegulatorJ. B. D. Soldera, Andre Vilas Boas, Alfredo Olmos. 177-180 [doi]
- A Temperature Compensated Fully Trimmable On-Chip IC OscillatorAlfredo Olmos. 181-186 [doi]
- Bias Dependence of Noise Correlation in MAGFETsFernando C. Castaldo, Joao Paulo C. Cajueiro, Carlos Alberto dos Reis. 187-190 [doi]
- A Charge Correction Cell for FGMOS-Based CircuitsEsther Rodríguez-Villegas, Alberto Yufera, Adoración Rueda. 191 [doi]
- Unified Theory to Build Cell-Level Transistor Networks from BDDsRenato E. B. Poli, Felipe Ribeiro Schneider, Renato P. Ribas, André Inácio Reis. 199-204 [doi]
- Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-LogicMauricio Ayala-Rincón, Rodrigo B. Nogueira, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein. 205-210 [doi]
- Runtime Analysis of Synchronous Programs for Low-Level Real-Time VerificationGeorge Logothetis, Klaus Schneider, C. Metzler. 211-216 [doi]
- A Consumer Report on BDD PackagesGeert Janssen. 217 [doi]
- A New Hybrid Parallel/Reconfigurable Architecture: The X4CP32Arnaldo Azevedo, Rodrigo Soares, Ivan Saraiva Silva. 225-230 [doi]
- Control Development for Mechatronic Systems with a Fully Reconfigurable Pipeline ArchitectureAchim Rettberg, Mauro Cesar Zanella, Thomas Lehmann, Ulrich Dierkes, Carsten Rustemeier. 231-236 [doi]
- Efficient Processor Instruction Set Extension by Asynchronous Reconfigurable Datapath IntegrationJürgen Becker, Alexander Thomas, Maik Scheer. 237-242 [doi]
- Situated Learning on FPGA for Superscalar Microprocessor Design EducationRyuichi Takahashi, Hajime Ohiwa. 243 [doi]
- On-Chip Decoupling Capacitor Optimization for Noise and Leakage ReductionHoward H. Chen, J. Scott Neely, Michael F. Wang, Gricel Co. 251-255 [doi]
- Minimum-Area Shield Insertion for Explicit Inductive Noise ReductionMohamed A. Elgamel, Magdy A. Bayoumi. 256-260 [doi]
- A New Continuous Switching Window Computation with Crosstalk NoiseJanet Meiling Wang, Pinhong Chen, Omar Hafiz. 261-266 [doi]
- Improving Simulated Annealing Placement by Applying Random and Greedy Mixed PerturbationsRenato Fernandes Hentschke, Ricardo Augusto da Luz Reis. 267 [doi]
- Future Design Tools for Platform FPGAsPatrick Lysaght. 275 [doi]
- Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and LimitationsJürgen Becker, Michael Hübner, Michael Ullmann. 283-288 [doi]
- Dynamic Reconfiguration Behavior Using Generic FPGAs and FPIDsRomanelli Lodron Zuim, Claudionor José Nunes Coelho Jr., Luiz Fernando Etrusco Moreira, Antônio Otávio Fernandes, José Monteiro da Mata, Diógenes Cecilio da Silva Jr.. 289 [doi]
- Improving Critical Path Identification in Functional Timing AnalysisDaniel Lima Ferrão, Gustavo Wilke, Ricardo Augusto da Luz Reis, José Luís Almada Güntzel. 297-302 [doi]
- A Transistor Sizing Method Applied to an Automatic Layout Generation ToolCristiano Santos, Gustavo Wilke, Cristiano Lazzari, Ricardo Reis, José Luís Almada Güntzel. 303 [doi]
- Analog IC Modules Design Using Trapezoidal Association of MOS Transistors in 0.35µm TechnologyAlessandro Girardi, Fernando da Rocha Paixão Cortes, Eric E. Fabris, Sergio Bampi. 311-316 [doi]
- Digital Background Calibration Technique for Pipeline ADCs with Multi-Bit StagesAntonio J. Ginés, Eduardo J. Peralías, Adoración Rueda. 317-322 [doi]
- Design Methodologies for High-Speed CMOS Photoreceiver Front-EndsFaress Tissafi-Drissi, Ian O Connor, Fabien Mieyeville, Frédéric Gaffiot. 323-328 [doi]
- Testing RF Signal Paths Using Spectral Analysis and SubsamplingMarcelo Negreiros, Erik Schüler, Luigi Carro, Altamiro Amadeu Susin. 329 [doi]
- Accurate Dependability Analysis of CAN-Based Networked SystemsJ. Pérez, Matteo Sonza Reorda, Massimo Violante. 337-342 [doi]
- ReCoNet: Modeling and Implementation of Fault Tolerant Distributed Reconfigurable HardwareChristian Haubelt, Dirk Koch, Jürgen Teich. 343-348 [doi]
- CACO-PS: A General Purpose Cycle-Accurate Configurable Power SimulatorAntonio C. S. Beck Filho, Júlio C. B. de Mattos, Flávio Rech Wagner, Luigi Carro. 349-354 [doi]
- From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case StudyNey Laert Vilar Calazans, Edson I. Moreno, Fabiano Hessel, Vitor M. da Rosa, Fernando Moraes, Everton Carara. 355 [doi]