Power-Efficient Dual-Supply 64kB L1 Caches in a 65nm CMOS Technology - researchr publication authors

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Brian Campbell, James Burnette, Naveen Javarappa, Vincent von Kaenel. Power-Efficient Dual-Supply 64kB L1 Caches in a 65nm CMOS Technology. In Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007, DoubleTree Hotel, San Jose, California, USA, September 16-19, 2007. pages 729-732, IEEE, 2007. [doi]

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