Brian Campbell, James Burnette, Naveen Javarappa, Vincent von Kaenel. Power-Efficient Dual-Supply 64kB L1 Caches in a 65nm CMOS Technology. In Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007, DoubleTree Hotel, San Jose, California, USA, September 16-19, 2007. pages 729-732, IEEE, 2007. [doi]
@inproceedings{CampbellBJK07,
title = {Power-Efficient Dual-Supply 64kB L1 Caches in a 65nm CMOS Technology},
author = {Brian Campbell and James Burnette and Naveen Javarappa and Vincent von Kaenel},
year = {2007},
doi = {10.1109/CICC.2007.4405834},
url = {http://dx.doi.org/10.1109/CICC.2007.4405834},
researchr = {https://researchr.org/publication/CampbellBJK07},
cites = {0},
citedby = {0},
pages = {729-732},
booktitle = {Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007, DoubleTree Hotel, San Jose, California, USA, September 16-19, 2007},
publisher = {IEEE},
isbn = {978-1-4244-1623-3},
}