22.1 A 12GS/s 12b 4× Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer

Yuefeng Cao, Minglei Zhang, Yan Zhu 0001, Rui Paulo Martins, Chi-Hang Chan. 22.1 A 12GS/s 12b 4× Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer. In IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024. pages 388-390, IEEE, 2024. [doi]

@inproceedings{CaoZZMC24,
  title = {22.1 A 12GS/s 12b 4× Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer},
  author = {Yuefeng Cao and Minglei Zhang and Yan Zhu 0001 and Rui Paulo Martins and Chi-Hang Chan},
  year = {2024},
  doi = {10.1109/ISSCC49657.2024.10454350},
  url = {https://doi.org/10.1109/ISSCC49657.2024.10454350},
  researchr = {https://researchr.org/publication/CaoZZMC24},
  cites = {0},
  citedby = {0},
  pages = {388-390},
  booktitle = {IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024},
  publisher = {IEEE},
  isbn = {979-8-3503-0620-0},
}