22.1 A 12GS/s 12b 4× Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer

Yuefeng Cao, Minglei Zhang, Yan Zhu 0001, Rui Paulo Martins, Chi-Hang Chan. 22.1 A 12GS/s 12b 4× Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer. In IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024. pages 388-390, IEEE, 2024. [doi]

Abstract

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