Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation - researchr publication authors

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Gregorio Cappuccino, Andrea Pugliese 0002, Giuseppe Cocorullo. Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation. In Vassilis Paliouras, Johan Vounckx, Diederik Verkest, editors, Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings. Volume 3728 of Lecture Notes in Computer Science, pages 329-336, Springer, 2005. [doi]

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