7-bit 2.56 GS/s folding ADC with nanometric compatible architecture by using a high dynamic I/O folding amplifier

Luis Antonio Carrillo-Martínez, Guillermo Espinosa Flores-Verdad. 7-bit 2.56 GS/s folding ADC with nanometric compatible architecture by using a high dynamic I/O folding amplifier. In 4th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2013, Cusco, Peru, February 27 - March 1, 2013. pages 1-4, IEEE, 2013. [doi]

Authors

Luis Antonio Carrillo-Martínez

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Guillermo Espinosa Flores-Verdad

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