Luis Antonio Carrillo-MartÃnez, Guillermo Espinosa Flores-Verdad. 7-bit 2.56 GS/s folding ADC with nanometric compatible architecture by using a high dynamic I/O folding amplifier. In 4th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2013, Cusco, Peru, February 27 - March 1, 2013. pages 1-4, IEEE, 2013. [doi]
@inproceedings{Carrillo-Martinez13,
title = {7-bit 2.56 GS/s folding ADC with nanometric compatible architecture by using a high dynamic I/O folding amplifier},
author = {Luis Antonio Carrillo-MartÃnez and Guillermo Espinosa Flores-Verdad},
year = {2013},
doi = {10.1109/LASCAS.2013.6518996},
url = {https://doi.org/10.1109/LASCAS.2013.6518996},
researchr = {https://researchr.org/publication/Carrillo-Martinez13},
cites = {0},
citedby = {0},
pages = {1-4},
booktitle = {4th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2013, Cusco, Peru, February 27 - March 1, 2013},
publisher = {IEEE},
isbn = {978-1-4673-4897-3},
}