IP Validation for FPGAs Using Hardware Object Technology

Steve Casselman, John Schewel, Christophe Beaumont. IP Validation for FPGAs Using Hardware Object Technology. In Patrick Lysaght, James Irvine, Reiner W. Hartenstein, editors, Field-Programmable Logic and Applications, 9th International Workshop, FPL 99, Glasgow, UK, August 30 - September 1, 1999, Proceedings. Volume 1673 of Lecture Notes in Computer Science, pages 487-494, Springer, 1999.

Abstract

Abstract is missing.