Hakan Cetinkaya, Ali Zeki, Alper Girgin, Enver Derun Karabeyoglu, Tufan Coskun Karalar. A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs. In 25th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2018, Bordeaux, France, December 9-12, 2018. pages 277-280, IEEE, 2018. [doi]
@inproceedings{CetinkayaZGKK18,
title = {A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs},
author = {Hakan Cetinkaya and Ali Zeki and Alper Girgin and Enver Derun Karabeyoglu and Tufan Coskun Karalar},
year = {2018},
doi = {10.1109/ICECS.2018.8618005},
url = {https://doi.org/10.1109/ICECS.2018.8618005},
researchr = {https://researchr.org/publication/CetinkayaZGKK18},
cites = {0},
citedby = {0},
pages = {277-280},
booktitle = {25th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2018, Bordeaux, France, December 9-12, 2018},
publisher = {IEEE},
isbn = {978-1-5386-9562-3},
}