A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection

Kwanyeob Chae, Jaegeun Song, Yoonjae Choi, Jiyeon Park, Billy Koo, Jihun Oh, Shinyoung Yi, Won Lee, Dongha Kim, Kyeongkeun Kang, Eunsu Kim, Juyoung Kim, Sanghune Park, Sungcheol Park, Mijung Noh, Hyo-Gyuem Rhew, Jongshin Shin. A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection. J. Solid-State Circuits, 59(1):231-242, January 2024. [doi]

@article{ChaeSCPKOYLKKKKPPNRS24,
  title = {A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection},
  author = {Kwanyeob Chae and Jaegeun Song and Yoonjae Choi and Jiyeon Park and Billy Koo and Jihun Oh and Shinyoung Yi and Won Lee and Dongha Kim and Kyeongkeun Kang and Eunsu Kim and Juyoung Kim and Sanghune Park and Sungcheol Park and Mijung Noh and Hyo-Gyuem Rhew and Jongshin Shin},
  year = {2024},
  month = {January},
  doi = {10.1109/JSSC.2023.3330485},
  url = {https://doi.org/10.1109/JSSC.2023.3330485},
  researchr = {https://researchr.org/publication/ChaeSCPKOYLKKKKPPNRS24},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {59},
  number = {1},
  pages = {231-242},
}