Multi-standard low-power DDR I/O circuit design in 7nm CMOS process

M. Chae, T. Wilson, Eric Naviasky. Multi-standard low-power DDR I/O circuit design in 7nm CMOS process. In IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017. pages 1-4, IEEE, 2017. [doi]

Authors

M. Chae

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T. Wilson

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Eric Naviasky

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