Multi-standard low-power DDR I/O circuit design in 7nm CMOS process

M. Chae, T. Wilson, Eric Naviasky. Multi-standard low-power DDR I/O circuit design in 7nm CMOS process. In IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017. pages 1-4, IEEE, 2017. [doi]

@inproceedings{ChaeWN17,
  title = {Multi-standard low-power DDR I/O circuit design in 7nm CMOS process},
  author = {M. Chae and T. Wilson and Eric Naviasky},
  year = {2017},
  doi = {10.1109/ISCAS.2017.8050331},
  url = {https://doi.org/10.1109/ISCAS.2017.8050331},
  researchr = {https://researchr.org/publication/ChaeWN17},
  cites = {0},
  citedby = {0},
  pages = {1-4},
  booktitle = {IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017},
  publisher = {IEEE},
  isbn = {978-1-4673-6853-7},
}