A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure - researchr publication authors

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Chi-Hang Chan, Yan Zhu 0001, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins. A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure. In Symposium on VLSI Circuits, VLSIC 2012, Honolulu, HI, USA, June 13-15, 2012. pages 86-87, IEEE, 2012. [doi]

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