Race logic synthesis for a multithreaded HDL/ESL simulator for SoC designs - researchr publication

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T. Chan. Race logic synthesis for a multithreaded HDL/ESL simulator for SoC designs. In 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2010, Kuala Lumpur, Malaysia, December 6-9, 2010. pages 1179-1182, IEEE, 2010. [doi]

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