G. Subash Chandar, S. Vaideeswaran. Addressing verification bottlenecks of fully synthesized processor cores using equivalence checkers. In Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan. pages 175-180, ACM, 2001. [doi]
@inproceedings{ChandarV01, title = {Addressing verification bottlenecks of fully synthesized processor cores using equivalence checkers}, author = {G. Subash Chandar and S. Vaideeswaran}, year = {2001}, doi = {10.1145/370155.370316}, url = {http://doi.acm.org/10.1145/370155.370316}, researchr = {https://researchr.org/publication/ChandarV01}, cites = {0}, citedby = {0}, pages = {175-180}, booktitle = {Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan}, publisher = {ACM}, isbn = {0-7803-6634-4}, }