Hsiu-Ming Chang, Chin-Hsuan Chen, Kuan-Yu Lin, Kwang-Ting Cheng. Calibration and Testing Time Reduction Techniques for a Digitally-Calibrated Pipelined ADC. In 27th IEEE VLSI Test Symposium, VTS 2009, May 3-7, 2009, Santa Cruz, California, USA. pages 291-296, IEEE Computer Society, 2009. [doi]
Abstract is missing.