Yu-Cheng Chang, Wei-Hao Chiu, Chen-Chien Lin, Tsung-Hsien Lin. A 4MHz BW 69dB SNDR continuous-time delta-sigma modulator with reduced sensitivity to clock jitter. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2011, Jeju, South Korea, November 14-16, 2011. pages 265-268, IEEE, 2011. [doi]
Abstract is missing.