Chip-Hong Chang, Jiangmin Gu, Mingyan Zhang. A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits. IEEE Trans. VLSI Syst., 13(6):686-695, 2005. [doi]
@article{ChangGZ05,
title = {A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits},
author = {Chip-Hong Chang and Jiangmin Gu and Mingyan Zhang},
year = {2005},
doi = {10.1109/TVLSI.2005.848806},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2005.848806},
tags = {reviewing},
researchr = {https://researchr.org/publication/ChangGZ05},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {13},
number = {6},
pages = {686-695},
}