A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits

Chip-Hong Chang, Jiangmin Gu, Mingyan Zhang. A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits. IEEE Trans. VLSI Syst., 13(6):686-695, 2005. [doi]

Abstract

Abstract is missing.