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Kwuang-Han Chang, Chih-Cheng Hsieh. A Calibration-Free 12-bit 50-MS/s Full-Analog SAR ADC With Feedback Zero-Crossing Detectors. J. Solid-State Circuits, 54(6):1624-1635, 2019. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: A 12-bit 40-MS/s calibration-free SAR ADCChung-Wei Hsu, Li-Jen Chang, Chun-Po Huang, Soon-Jyh Chang. iscas 2017: 1-4 [doi] A Calibration-Free 13-Bit 10-MS/s Full-Analog SAR ADC With Continuous-Time Feedforward Cascaded Op-AmpsKwuang-Han Chang, Chih-Cheng Hsieh. jssc, 54(10):2691-2702, 2019. [doi] A 40MS/s 12-bit Zero-Crossing Based SAR-Assisted Two-Stage Pipelined ADC with Adaptive Level ShiftingYung-Te Chang, Min-Rui Wu, Chih-Cheng Hsieh. iscas 2019: 1-4 [doi]
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