Paged cache: an efficient partition architecture for reducing power, area and access time - researchr publication authors

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Yen-Jen Chang, Feipei Lai. Paged cache: an efficient partition architecture for reducing power, area and access time. In IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002. pages 473-478, IEEE, 2002. [doi]

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