Yen-Jen Chang, Feipei Lai. Paged cache: an efficient partition architecture for reducing power, area and access time. In IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002. pages 473-478, IEEE, 2002. [doi]
@inproceedings{ChangL02:4,
title = {Paged cache: an efficient partition architecture for reducing power, area and access time},
author = {Yen-Jen Chang and Feipei Lai},
year = {2002},
doi = {10.1109/APCCAS.2002.1115309},
url = {http://dx.doi.org/10.1109/APCCAS.2002.1115309},
tags = {caching, architecture, partitioning},
researchr = {https://researchr.org/publication/ChangL02%3A4},
cites = {0},
citedby = {0},
pages = {473-478},
booktitle = {IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002},
publisher = {IEEE},
}