Zero-aware asymmetric SRAM cell for reducing cache power in writing zero

Yen-Jen Chang, Feipei Lai, Chia-Lin Yang. Zero-aware asymmetric SRAM cell for reducing cache power in writing zero. IEEE Trans. VLSI Syst., 12(8):827-836, 2004. [doi]

Authors

Yen-Jen Chang

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Feipei Lai

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Chia-Lin Yang

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