Designing ultra-low voltage PLL Using a bulk-driven technique - researchr publication authors

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Ting-Sheng Chao, Yu-lung Lo, Wei-Bin Yang, Kuo-Hsing Cheng. Designing ultra-low voltage PLL Using a bulk-driven technique. In 35th European Solid-State Circuits Conference, ESSCIRC 2009, Athens, Greece, 14-18 September 2009. pages 388-391, IEEE, 2009. [doi]

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