Bhaskar Chatterjee, Manoj Sachdev. Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology. IEEE Trans. VLSI Syst., 13(11):1296-1304, 2005. [doi]
@article{ChatterjeeS05:0,
title = {Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology},
author = {Bhaskar Chatterjee and Manoj Sachdev},
year = {2005},
doi = {10.1109/TVLSI.2005.859563},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2005.859563},
tags = {testing, design},
researchr = {https://researchr.org/publication/ChatterjeeS05%3A0},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {13},
number = {11},
pages = {1296-1304},
}