Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology

Bhaskar Chatterjee, Manoj Sachdev. Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology. IEEE Trans. VLSI Syst., 13(11):1296-1304, 2005. [doi]

Abstract

Abstract is missing.