Biman Chattopadhyay, Anant S. Kamath, Satyasai Evani, Karthik Subburaj. A 2GHz Digital PLL, with temperature lock range of -40°C to 125°C, in 45nm CMOS. In Rakesh Patel, Tom Andre, Aurangzeb Khan, editors, 2011 IEEE Custom Integrated Circuits Conference, CICC 2011, San Jose, CA, USA, Sept. 19-21, 2011. pages 1-4, IEEE, 2011. [doi]
Abstract is missing.