Subhomoy Chattopadhyay, Rakesh Patel. Tutorial T3: Low Power Design Techniques for Nanometer Design Processes - 65nm and Smaller. In 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India. pages 5, IEEE Computer Society, 2007. [doi]
@inproceedings{ChattopadhyayP07,
title = {Tutorial T3: Low Power Design Techniques for Nanometer Design Processes - 65nm and Smaller},
author = {Subhomoy Chattopadhyay and Rakesh Patel},
year = {2007},
doi = {10.1109/VLSID.2007.167},
url = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.167},
tags = {design},
researchr = {https://researchr.org/publication/ChattopadhyayP07},
cites = {0},
citedby = {0},
pages = {5},
booktitle = {20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India},
publisher = {IEEE Computer Society},
isbn = {0-7695-2502-4},
}