Atanu Chattopadhyay, Zeljko Zilic. GALDS: a complete framework for designing multiclock ASICs and SoCs. IEEE Trans. VLSI Syst., 13(6):641-654, 2005. [doi]
@article{ChattopadhyayZ05,
title = {GALDS: a complete framework for designing multiclock ASICs and SoCs},
author = {Atanu Chattopadhyay and Zeljko Zilic},
year = {2005},
doi = {10.1109/TVLSI.2005.848825},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2005.848825},
tags = {completeness},
researchr = {https://researchr.org/publication/ChattopadhyayZ05},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {13},
number = {6},
pages = {641-654},
}