Cyrille Chavet, Philippe Coussy. A memory mapping approach for parallel interleaver design with multiples read and write accesses. In International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France. pages 3168-3171, IEEE, 2010. [doi]
@inproceedings{ChavetC10, title = {A memory mapping approach for parallel interleaver design with multiples read and write accesses}, author = {Cyrille Chavet and Philippe Coussy}, year = {2010}, doi = {10.1109/ISCAS.2010.5537955}, url = {http://dx.doi.org/10.1109/ISCAS.2010.5537955}, tags = {design, systematic-approach}, researchr = {https://researchr.org/publication/ChavetC10}, cites = {0}, citedby = {0}, pages = {3168-3171}, booktitle = {International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France}, publisher = {IEEE}, }