Chak-Fong Cheang, Pui-In Mak, Rui P. Martins. A Hardware-Efficient Feedback Polynomial Topology for DPD Linearization of Power Amplifiers: Theory and FPGA Validation. IEEE Trans. on Circuits and Systems, 65(9):2889-2902, 2018. [doi]
@article{CheangMM18,
title = {A Hardware-Efficient Feedback Polynomial Topology for DPD Linearization of Power Amplifiers: Theory and FPGA Validation},
author = {Chak-Fong Cheang and Pui-In Mak and Rui P. Martins},
year = {2018},
doi = {10.1109/TCSI.2017.2788082},
url = {https://doi.org/10.1109/TCSI.2017.2788082},
researchr = {https://researchr.org/publication/CheangMM18},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on Circuits and Systems},
volume = {65},
number = {9},
pages = {2889-2902},
}