A Hardware-Efficient Feedback Polynomial Topology for DPD Linearization of Power Amplifiers: Theory and FPGA Validation - researchr publication

researchr

You are not signed in
Sign in
Sign up

Chak-Fong Cheang, Pui-In Mak, Rui P. Martins. A Hardware-Efficient Feedback Polynomial Topology for DPD Linearization of Power Amplifiers: Theory and FPGA Validation. IEEE Trans. on Circuits and Systems, 65(9):2889-2902, 2018. [doi]

Abstract is missing.

runs on WebDSL