Design of a High Speed, Low Latency and Low Power Consumption DRAM Using two-transistor Cell Structure - researchr publication authors

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Amin Chegeni, Khayrollah Hadidi, Abdollah Khoei. Design of a High Speed, Low Latency and Low Power Consumption DRAM Using two-transistor Cell Structure. In 14th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2007, Marrakech, Morocco, December 11-14, 2007. pages 1167-1170, IEEE, 2007. [doi]

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