Amin Chegeni, Khayrollah Hadidi, Abdollah Khoei. Design of a High Speed, Low Latency and Low Power Consumption DRAM Using two-transistor Cell Structure. In 14th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2007, Marrakech, Morocco, December 11-14, 2007. pages 1167-1170, IEEE, 2007. [doi]
@inproceedings{ChegeniHK07,
title = {Design of a High Speed, Low Latency and Low Power Consumption DRAM Using two-transistor Cell Structure},
author = {Amin Chegeni and Khayrollah Hadidi and Abdollah Khoei},
year = {2007},
doi = {10.1109/ICECS.2007.4511203},
url = {http://dx.doi.org/10.1109/ICECS.2007.4511203},
researchr = {https://researchr.org/publication/ChegeniHK07},
cites = {0},
citedby = {0},
pages = {1167-1170},
booktitle = {14th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2007, Marrakech, Morocco, December 11-14, 2007},
publisher = {IEEE},
isbn = {978-1-4244-1377-5},
}