William N. Chelton, Mohammed Benaissa. High-Speed Pipelined EGG Processor on FPGA. In Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada. pages 136-141, IEEE, 2006. [doi]
@inproceedings{CheltonB06,
title = {High-Speed Pipelined EGG Processor on FPGA},
author = {William N. Chelton and Mohammed Benaissa},
year = {2006},
doi = {10.1109/SIPS.2006.352569},
url = {http://dx.doi.org/10.1109/SIPS.2006.352569},
researchr = {https://researchr.org/publication/CheltonB06},
cites = {0},
citedby = {0},
pages = {136-141},
booktitle = {Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada},
publisher = {IEEE},
isbn = {1-4244-0382-0},
}