Table of Contents

• Molecular quantum-dot cellular automataCraig S. Lent. [doi]
• Signal Processing Based Implantable Microsystems for Intracortical Therapeutic PurposesMohamad Sawan. [doi]
• Design of high performance timing recovery loops for communication applicationsV. Torres, A. Perez-Pascual, T. Sansaloni, Javier Valls. 1-4 [doi]
• Automating the Verification of SDR Base band Signal Processing Algorithms Developed on DSP/FPGA PlatformAndrew K. C. Kwan, Slim Boumaiza, Michael R. Smith, Fadhel M. Ghannouchi. 5-9 [doi]
• Configuration and Representation of Large-Scale Dataflow Graphs using the Dataflow Interchange FormatIvan Corretjer, Chia-Jui Hsu, Shuvra S. Bhattacharyya. 10-15 [doi]
• Exploit Multiple-Domain Sparseness for HSDPA Chip Level Equalization in SDR: Algorithm and DSP ImplementationMin Li, Bruno Bougard, Francky Catthoor. 16-21 [doi]
• Design and Implementation of Turbo Decoders for Software Defined RadioYuan Lin, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Alastair Reid, Krisztián Flautner. 22-27 [doi]
• Low Complexity List Updating Circuits for List Sphere DecodersYuping Zhang, Jun Tang, Keshab K. Parhi. 28-33 [doi]
• Performance Analysis of a New Transmission Scheme for Multi-Relay ChannelsMohamed Elfituri, Walaa Hamouda, Ali Ghrayeb. 34-38 [doi]
• A Reconfigurable SOS-based Rayleigh Fading Channel SimulatorAmirhossein Alimohammad, Bruce F. Cockburn. 39-44 [doi]
• Low complexity iterative joint detection, decoding, and channel estimation for wireless MIMO systemJian-Hung Lin, Keshab K. Parhi. 45-50 [doi]
• Maximum Likelihood Estimation of Carrier Frequency Offset in Correlated MIMO OFDM SystemsXiang Nian Zeng, Ali Ghrayeb. 51-55 [doi]
• Reduced-Complexity Pipelined Architectures for Finite Field InversionsZhiyuan Yan, Dilip V. Sarwate. 56-61 [doi]
• Rapid IP Design of Variable-length Cached-FFT Processor for OFDM-based Communication SystemsYu-Hung Lee, Tzu-Hao Yu, Kuo-Ken Huang, An-Yeu Wu. 62-65 [doi]
• A Structural Study and Hyperedge Clustering Technique for Large Scale CircuitsLogan M. Rakai, Jianhua Li, Laleh Behjat, Jie Huang. 66-70 [doi]
• Performance Evaluation of an SIMD Architecture with a Multi-bank Vector Memory UnitHoseok Chang, Junho Cho, Wonyong Sung. 71-76 [doi]
• A Reduced-Complexity, Scalable Implementation of Low Density Parity Check (LDPC) DecoderYuming Zhu, Yanni Chen, Dale E. Hocevar, Manish Goel. 83-88 [doi]
• A New Early Termination Scheme of Iterative Turbo Decoding Using Decoding ThresholdFan-Min Li, Cheng-Hung Lin, An-Yeu Wu. 89-94 [doi]
• Pipelined ALU for Signal Processing to Implement Interval ArithmeticRuchir Gupte, William W. Edmonson, Senanu Ocloo, Winser E. Alexander. 95-100 [doi]
• H.264 Video Encoder Implementation on a Low-power DSP with Low and Stable Computational ComplexityKenji Goto, Atsushi Hatabu, Hirofumi Nishizuka, Katsumasa Matsunaga, Ryoichi Nakamura, Yoji Mochizuki, Takashi Miyazaki. 101-106 [doi]
• H.264 Video Decoder Design: Beyond RTL Design ImplementationYoungsoo Kim, William Edmonson. 107-112 [doi]
• An Iterative Method for Frame-Level Adaptive Wiener Interpolation Filters in Video CodingJianpeng Dong, Nam Ling. 113-117 [doi]
• A Theoretical Model and Study of Weighted MCTF Residual EnergyFengling Li, Nam Ling, Stephen A. Chiappari. 118-123 [doi]
• VSIP : Video Specific Instruction Set Processor for H.264/AVCKwang-Woo Lee, Sung Dae Kim, Myung Hoon Sunwoo. 124-129 [doi]
• Motion Compensated Frame Rate Conversion Using a Specialized Instruction Set ProcessorNicolas Beucher, Normand Bélanger, Yvon Savaria, Guy Bois. 130-135 [doi]
• High-Speed Pipelined EGG Processor on FPGAWilliam N. Chelton, Mohammed Benaissa. 136-141 [doi]
• A Reconfigurable Applcation Specific Instruction Set Processor for Viterbi and Log-MAP DecodingTimo Vogt, Norbert Wehn. 142-147 [doi]
• Limiting Flexibility in Multiplication over GF(2m): A Design MethodologyWilliam N. Chelton, Mohammed Benaissa. 153-156 [doi]
• 0.35 m 22W Multiphase Programmable Clock Generator for Circular Memory SC FIR Filter For Wireless Sensor ApplicationsRafal Dlugosz, Krzysztof Iniewski, Tomasz Talaska. 157-160 [doi]
• Semi-Blind Channel Estimation for OFDM using Least SquaresJarlath Ifiok Umoh, Tokunbo Ogunfunmi. 161-164 [doi]
• A Robust Band-Tracking Packet Detector (BT-PD) in OFDM-Based Ultra-Wideband SystemsJyh-Ting Lai, Chun-Yuan Chu, An-Yeu Wu, Wen-Chiang Chen. 165-170 [doi]
• A Low Cost Packet Detector in OFDM-Based Ultra-Wideband SystemsJyh-Ting Lai, Chun-Yuan Chu, An-Yeu Wu, Wen-Chiang Chen. 171-176 [doi]
• EM-based Channel Estimation for Space Time Block Coded MIMO OFDM SystemsHaideh M. Karkhanechi, Bernard C. Levy. 177-181 [doi]
• FPGA Implementation of Pipelined Architecture for Optical Imaging Distortion CorrectionLin Qiang, Nigel M. Allinson. 182-187 [doi]
• A Low-Power Folded Programmable FIR ArchitectureLi-Hsun Chen, Oscal T.-C. Chen. 188-193 [doi]
• An Examination of the Effect of Feature Size Scaling on Effective Power Consumption in Analog to Digital ConvertersKeith Boyle, Sai Mohan Kilambi, Rafal Dlugosz, Kris Iniewski, Vincent C. Gaudet. 194-199 [doi]
• Low-Power Saturated Arithmetic and its Application in VLSI Architectures for OFDM ModemsKonstantina Karagianni, Vassilis Paliouras, Theodoros Giannopoulos. 200-204 [doi]
• Low Power Trellis Decoder with Overscaled Supply VoltageYang Liu, Tong Zhang, Jiang Hu. 205-208 [doi]
• Simplified Criteria for Early Iterative Decoding TerminationSpyros Gidaros, Vassilis Paliouras. 209-214 [doi]
• Fixed-to-Variable Length Source Coding Using Turbo CodesJavad Haghighat, Walaa Hamouda, M. Reza Soleymani. 215-219 [doi]
• Partly Parallel Overlapped Sum-Product Decoder Architectures for Quasi-Cyclic LDPC CodesNing Chen, Yongmei Dai, Zhiyuan Yan. 220-225 [doi]
• On the Effects of Colored Noise on the Performance of LDPC CodesSaeed Sharifi Tehrani, Bruce F. Cockburn, Stephen Bates. 226-231 [doi]
• An Optimal Adaptive M-PSK Carrier Phase Detector Suitable for Fixed-Point Hardware Implementation within FPGAs and ASICsYair Linn. 232-237 [doi]
• Automated derivation of NoC Communication Specifications from Application ConstraintsSamuel Evain, Jean-Philippe Diguet, Milad El Khodary, Dominique Houzet. 238-243 [doi]
• Design Space Exploration of DSP Applications Based on Behavioral Description ModelsFarhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin. 244-249 [doi]
• Evaluating SoC Network Performance in MPEG-4 EncoderAri Kulmala, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen. 250-255 [doi]
• Transparent Embedded Compression in Systems-on-ChipA. K. Riemens, René J. van der Vleuten, Pieter van der Wolf, G. Jacob, Jan-Willem van de Waerdt, J. G. Janssen. 256-261 [doi]
• Low Complexity Implementations of Sum-Product Algorithm for Decoding Low-Density Parity-Check CodesDaesun Oh, Keshab K. Parhi. 262-267 [doi]
• Spatial Optical Distortion Correction in an FPGALin Qiang, Nigel M. Allinson. 268-273 [doi]
• Automated Architectural Exploration for Signal Processing AlgorithmsRamsey Hourani, Ravi Jenkal, W. Rhett Davis, Winser Alexander. 274-279 [doi]
• Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing SystemsCaaliph Andriamisaina, Bertrand Le Gal, Emmanuel Casseau. 280-285 [doi]
• Automatic Generation of Programmable Parallel CRC & Scrambler DesignsYin-Tsung Hwang, Jiun-Yan Chen, Ming-Hwa Sheu. 286-291 [doi]
• Instruction Transfer And Storage Exploration for Low Energy VLIWsTom Vander Aa, Murali Jayapala, Henk Corporaal, Francky Catthoor, Geert Deconinck. 292-297 [doi]
• Fault Tolerance of Quantized Unitary PrecodersAli Yazdanpanah, Rodney G. Vaughan. 298-302 [doi]
• Low-Power High-Throughput BCH Error Correction VLSI Design for Multi-Level Cell NAND Flash MemoriesWei Liu, Junrye Rho, Wonyong Sung. 303-308 [doi]
• A Shortened Impulse Response Filter (SIRF) Scheme for Cost-Effective Echo Canceller Design of 10GBase-T Ethernet SystemMing-Feng Hsu, Yen-Liang Chen, Kai-Yuan Jheng, An-Yeu Wu. 309-312 [doi]
• On the Convergence of the Frequency-Domain LMS Adaptive Filter using LMS-DFTTokunbo Ogunfunmi, Thomas Paul. 313-320 [doi]
• FPGA Implementation of Adaptive Filters based on GSFAP using Log ArithmeticMilan Tichý, Jan Schier, David Gregg. 321-326 [doi]
• SystemC Model of an Interoperative GPS/Galileo Code Correlator ChannelHeikki Hurskainen, Jari Nurmi. 327-332 [doi]
• Desing and Optimization of a Programmable Instruction Decoder for DSP ArchitectureYong-Kyu Jung. 333-338 [doi]
• Carry Prediction and Selection for Truncated MultiplicationRomain Michard, Arnaud Tisserand, Nicolas Veyrat-Charvillon. 339-344 [doi]
• Carry Estimation for Two s Complement Fixed-Width MultipliersYen-Chin Liao, Hsie-Chia Chang, Chih-Wei Liu. 345-350 [doi]
• Subword-Parallel VLIW Architecture Exploration for Multimode Software Defined RadioThomas Schuster, D. N. Bruna, Bruno Bougard, V. Derudder, A. Hoffmann, Liesbet Van der Perre. 351-356 [doi]
• On The Identification of Snow Movements on RoadsJun Cai, Muzamil S. Pervez, Mohamed S. Shehata, Robert Johannesson, Wael M. Badawy, Ahmad Radmanesh. 357-361 [doi]
• Software-Controlled Scratchpad Mapping Strategies for Wavelet-Based ApplicationsBert Geelen, Aris Ferentinos, Francky Catthoor, Arnout Vandecappelle, Gauthier Lafruit, Thanos Stouraitis, Rudy Lauwereins, Diederik Verkest. 362-367 [doi]
• An Area Efficient Real-time CAVLC IP-Block towards the H.264/AVC EncoderChoudhury A. Rahman, Wael M. Badawy. 368-371 [doi]
• Efficient Memory Reuse and Sub-Pixel Interpolation Algorithms for ME/MC of H.264/AVCChoong Jin Hyun, Sung Dae Kim, Myung Hoon Sunwoo. 377-382 [doi]
• An Efficient Data Reuse Motion Estimation EngineSumeer Goel, Yasser Ismail, Parimal Devulapalli, Jason McNeely, Magdy A. Bayoumi. 383-386 [doi]
• A VLSI 8×8 MIMO Near-ML Decoder EngineGeoff Knagge, Mark Bickerstaff, Brett Ninness, Steven R. Weller, Graerne Woodward. 387-392 [doi]
• An Energy-Efficient Reconfigurable Baseband Processor for Flexible RadiosAda S. Y. Poon. 393-398 [doi]
• SmartMIMO: Energy-Aware Adaptive MIMO-OFDM Radio Link Control for Wireless Local Area NetworksBruno Bougard, Gregory Lenoir, Antoine Dejonghe, Liesbet Van der Perre, Francky Catthoor, Wim Dehaene. 399-404 [doi]
• Architecture-Aware LDPC Code Design for Software Defined RadioYuming Zhu, Chaitali Chakrabarti. 405-410 [doi]
• Adaptive Tap Management in Multi-Gigabit Echo & Next CancellersJie Chen, Keshab K. Parhi. 411-415 [doi]
• Analog-Counter-Based Conscience Mechanism in Kohonen s Neural Network Implemented in CMOS 0.18 m TechnologyTomasz Talaska, Ryszard Wojtyna, Rafal Dlugosz, Krzysztof Iniewski, Witold Pedrycz. 416-421 [doi]
• On-Line MSR-CORDIC VLSI Architecture with Applications to Cost-Efficient Rotation-Based Adaptive Filtering SystemsTzu-Hao Yu, Chi-Li Yu, Kai-Yuan Jheng, An-Yeu Wu. 422-427 [doi]
• Design and Implementation of JPEG 2000 Codec with Bit-Plane Scalable ArchitectureYu-wei Chang, Chih-Chi Cheng, Chun-Chia Chen, Hung-Chi Fang, Liang-Gee Chen. 428-433 [doi]
• A Low-Complexity PTS-based PAPR Reduction Technique for OFDM Signals without Transmission of Side InformationTheodoros Giannopoulos, Vassilis Paliouras. 434-439 [doi]