Low-Power High-Throughput BCH Error Correction VLSI Design for Multi-Level Cell NAND Flash Memories

Wei Liu, Junrye Rho, Wonyong Sung. Low-Power High-Throughput BCH Error Correction VLSI Design for Multi-Level Cell NAND Flash Memories. In Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada. pages 303-308, IEEE, 2006. [doi]

Abstract

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