A Sub-Sampling 35GHz PLL in 45nm PDSOI BiCMOS with 37fs Integrated Jitter and a FoM of -252dB

Christopher Chen, Yan Zhang 0050, Hao-Yu Chien, Jiazhang Song, Jia Zhou, Chao-Jen Tien, Sudhakar Pamarti, Chih-Kong Ken Yang, Mau-Chung Frank Chang. A Sub-Sampling 35GHz PLL in 45nm PDSOI BiCMOS with 37fs Integrated Jitter and a FoM of -252dB. In IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, BCICTS 2024, Fort Lauderdale, FL, USA, October 27-30, 2024. pages 203-206, IEEE, 2024. [doi]

Abstract

Abstract is missing.