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Chien-In Henry Chen. Graph Partitioning for Concurrent Test Scheduling in VLSI Circuit. In DAC. pages 287-290, 1991. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Partitioning Techniques for Built-In Self-Test DesignChien-In Henry Chen. vlsi, 2(3):185-198, 1994. [doi] Configurable 2-D Linear Feedback Shift Registers for VLSI Built-in Self-test DesignsChien-In Henry Chen, Yingjie Zhou. vlsi, 2000(2):149-159, 2000. [doi]
The following publications are possibly variants of this publication: