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Yan-Jiun Chen, Kwuang-Han Chang, Chih-Cheng Hsieh. A 2.02-5.16 fJ/Conversion Step 10 Bit Hybrid Coarse-Fine SAR ADC With Time-Domain Quantizer in 90 nm CMOS. J. Solid-State Circuits, 51(2):357-364, 2016. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: A 0.4 V 1.94 fJ/conversion-step 10 bit 750 kS/s SAR ADC with Input-Range-Adaptive SwitchingPei-Chen Lee, Jin-Yi Lin, Chih-Cheng Hsieh. tcas, 63-I(12):2149-2157, 2016. [doi] A 0.4V 2.02fJ/conversion-step 10-bit hybrid SAR ADC with time-domain quantizer in 90nm CMOSYan-Jiun Chen, Chih-Cheng Hsieh. vlsic 2014: 1-2 [doi]
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