Boosting the Performance of 3D Charge Trap NAND Flash with Asymmetric Feature Process Size Characteristic - researchr publication authors

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Shuo-Han Chen, Yen-Ting Chen, Hsin-Wen Wei, Wei Kuan Shih. Boosting the Performance of 3D Charge Trap NAND Flash with Asymmetric Feature Process Size Characteristic. In Proceedings of the 54th Annual Design Automation Conference, DAC 2017, Austin, TX, USA, June 18-22, 2017. ACM, 2017. [doi]

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