A novel RISC-V core for the networking processing processor with bit-level custom instructions and thread-aware fetching architecture - researchr publication

researchr

You are not signed in
Sign in
Sign up

Jiakun Chen, Yuanming Fu, Yuyu Lian, Jianhui Han, Jianyuan Pi, Ming Ling. A novel RISC-V core for the networking processing processor with bit-level custom instructions and thread-aware fetching architecture. Integration, 109:102749, 2026. [doi]

Abstract is missing.

runs on WebDSL