Low-power gated clock tree optimization for three-dimensional integrated circuits

Yu-chuan Chen, Chih-Cheng Hsu, Mark Po-Hung Lin. Low-power gated clock tree optimization for three-dimensional integrated circuits. In VLSI Design, Automation and Test, VLSI-DAT 2015, Hsinchu, Taiwan, April 27-29, 2015. pages 1-4, IEEE, 2015. [doi]

Authors

Yu-chuan Chen

This author has not been identified. Look up 'Yu-chuan Chen' in Google

Chih-Cheng Hsu

This author has not been identified. Look up 'Chih-Cheng Hsu' in Google

Mark Po-Hung Lin

This author has not been identified. Look up 'Mark Po-Hung Lin' in Google