Yung-Chih Chen, Wei-An Ji, Chih-Chung Wang, Ching-Yi Huang, Chia-Cheng Wu, Chia-Chun Lin, Chun-Yao Wang. Using range-equivalent circuits for facilitating bounded sequential equivalence checking. In 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 16-19, 2018. pages 1-4, IEEE, 2018. [doi]
Abstract is missing.