A Simulation Study of Scaling Capability toward 10nm for the 3D Stackable Gate-Controlled Thyristor (GCT) DRAM Device - researchr publication authors

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Wei-Chen Chen, Hang-Ting Lue, Tzu-Hsuan Hsu, Keh-Chung Wang, Chih-Yuan Lu. A Simulation Study of Scaling Capability toward 10nm for the 3D Stackable Gate-Controlled Thyristor (GCT) DRAM Device. In IEEE International Memory Workshop, IMW 2023, Monterey, CA, USA, May 21-24, 2023. pages 1-4, IEEE, 2023. [doi]

This author has not been identified. Look up 'Wei-Chen Chen' in GoogleThis author has not been identified. Look up 'Hang-Ting Lue' in GoogleThis author has not been identified. Look up 'Tzu-Hsuan Hsu' in GoogleThis author has not been identified. Look up 'Keh-Chung Wang' in GoogleThis author has not been identified. Look up 'Chih-Yuan Lu' in Google

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