Table of Contents

• Voltage Control of Magnetism: Low-Power SpintronicsAstha Khandelwal, Rajesh Chopdekar, Akash Surampalli, Kaushal Tiwari, Naveen Negi, Alan Kalitsov, Lei Wan, Jordan A. Katine, Derek Stewart 0003, Tiffany S. Santos, Yen-Lin Huang, Ramamoorthy Ramesh, Bhagwati Prasad. 1-4 [doi]
• A Comprehensive Study on the Pillar Size of OTS-PCM Memory with an Optimized Process and Scaling Trends Down to Sub-10 nm for SCM ApplicationsWei-Chih Chien, E. K. Lai, L. Buzi, C. W. Cheng, C. W. Yeh, A. Ray, L. M. Gignac, N. Gong, H. Y. Cheng, A. Grun, D. Y. Lee, W. Kim, A. Majumdar, Douglas M. Bishop, Robert L. Bruce, D. Daudelin, H. Y. Ho, M. J. BrightSky, H. L. Lung. 1-4 [doi]
• Comprehensive Study of Endurance Fatigue in the Scaled Si FeFET by in-situ Vth Measurement and Endurance Enhancement StrategyXianzhou Shao, Junshuai Chai, Min Liao, Jiahui Duan, Fengbin Tian, Xiaoyu Ke, Xiaoqing Sun, Hao Xu, Jinjuan Xiang, Xiaolei Wang, Wenwu Wang 0006. 1-4 [doi]
• 2 DRAM ArchitectureDaohuan Feng, Yi Jiang, Yunsong Qiu, Yuhong Zheng, Harry Kim, JaeWoo Kim, Jian Chu, Guangsu Shao, Yucheng Liao, Chen Yang, Minrui Hu, Wenli Zhao, Linjiang Xia, Jianfeng Xiao, Di Ma, Yuan Cheng, Xiangbo Kong, Chao Lin, Tianming Li, Yongjie Li, Jingheng Meng, Kai Shao, Yan Wang, Xiaoan Yang, Xiang Liu, Qinghua Han, Huiming Li, Yanzhe Tang, Mingde Liu, Eric Wu, Xiaoping Li, Renrui Huang, Mingtang Zhang, Long Hou, Xuan Pan, Xinwen Jin, Shuiping Zhao, Dh Han, Ted Park, Deyuan Xiao, Chao Zhao, Abraham Yoo. 1-4 [doi]
• Distributed Cycling in Charge Trap-Based 3D NAND Arrays: Model and Qualification Tests ImplicationsGianluca Nicosia, Niccolò Righetti, Yingda Dong. 1-4 [doi]
• A 3D Stackable 1T1C DRAM: Architecture, Process Integration and Circuit SimulationMeng Huang, Shufang Si, Zheng He, Ying Zhou, Sijia Li, Hong Wang, Jinying Liu, Dongsheng Xie, Mengmeng Yang, Kang You, Chris Choi, Yi Tang, Xiaojie Li, Shibing Qian, Xiaodong Yang, Long Hou, Weiping Bai, Zhongming Liu, Yanzhe Tang, Qiong Wu, Yanqin Wang, Tao Dou, Jake Kim, Guilei Wang, Jie Baisp, Adachi Takao, Chao Zhao, Abraham Yoo. 1-4 [doi]
• Demonstration of SMT-reflow Immune and SCA-resilient PUF on 28nm RRAM device arrayVivek Parmar, Sandeep Kaur Kingra, Deepak Verma, Digamber Pandey, Giuseppe Piccolboni, Alessandro Bricalli, Amir Regev, Gabriel Pares, Laurent Grenouillet, Jean-François Nodin, Manan Suri. 1-4 [doi]
• Materials Enabled Memory Scaling and New ArchitecturesZhijun Chen, Fred Fishburn, Chang Seok Kang, Sony Varghese, Bala Haran. 1-4 [doi]
• Multi-Level Operation of Ferroelectric FET Memory Arrays for Compute-In-Memory ApplicationsFranz Müller 0001, Sourav De, Maximilian Lederer, Raik Hoffmann, Ricardo Olivo, Thomas Kämpfe, Konrad Seidel, Tarek Ali, Halid Mulaosmanovic, Stefan Dünkel, Johannes Müller, Sven Beyer, Gerald Gerlach. 1-4 [doi]
• Towards Improving Ionizing Radiation Tolerance of 3-D NAND Flash MemoryBiswajit Ray, Matchima Buddhanoy, Mondol Anik Kumar. 1-4 [doi]
• 28nm Data Memory with Embedded RRAM Technology in Automotive MicrocontrollersAlessandro Grossi, Matteo Coppetta, Stefano Aresu, Andreas Kux, Thomas Kern, Robert Strenz. 1-4 [doi]
• Enabling 3D NAND Trench Cells for Scaled Flash MemoriesS. Rachidi, S. Ramesh, L. Breuil, Z. Tao, Devin Verreck, G. L. Donadio, Antonio Arreghini, G. Van den bosch, Maarten Rosmeulen. 1-4 [doi]
• 7-Bit/2Cell (X3.5), 9-Bit/2Cell (X4.5) NAND Flash Memory: Half Bit technologyNoboru Shibata, Hironori Uchikawa, Taira Shibuya, Kenri Nakai, Kosuke Yanagidaira, Hirofumi Inoue. 1-4 [doi]
• Proposal of P-Channel FE NAND with High Drain Current and Feasible Disturbance for Next Generation 3D NANDSong-Hyeon Kuk, Jae Hoon Han, Bong-Ho Kim, Junpyo Kim, Sang-Hyeon Kim. 1-4 [doi]
• Analog Tuning of Floating-Gate Cells with Sub-Elementary Charge Accuracy for In-Memory Computing ApplicationsYuri Tkachev, Steven Lemke, Louisa Schneider, Gilles Festes, Parviz Ghazavi. 1-4 [doi]
• Hafnium oxide-based Ferroelectric Memories: Are we ready for Application?Konrad Seidel, David Lehninger, Franz Müller 0001, Yannick Raffel, Ayse Sünbül, Ricardo Revello, Raik Hoffmann, Sourav De, Thomas Kämpfe, Maximilian Lederer. 1-4 [doi]
• Recent Technology Insights on STT-MRAM: Structure, Materials, and Process IntegrationJeongdong Choe. 1-4 [doi]
• Design of Ferroelectric-Metal Field-Effect Transistor for Multi-Level-Cell 3D NAND FlashSola Woo, Gihun Choe, Asif Islam Khan, Suman Datta, Shimeng Yu. 1-4 [doi]
• Physical Model and Characteristics of 3D NAND Memory Cell Metastability Issues under High Temperature StressAndrew Bicksler, Carmine Miccoli, Srinath Venkatesan. 1-4 [doi]
• Eliminating Capacitive Sneak Paths in Associative Capacitive Networks based on Complementary Resistive Switches for In-Memory ComputingTobias Ziegler 0005, Leon Brackmann, Tyler Hennen, Christopher Bengel, Stephan Menzel, Dirk J. Wouters. 1-4 [doi]
• Physical modeling and design rules of analog Conductive Metal Oxide-HfO2 ReRAMDonato Francesco Falcone, Stephan Menzel, Tommaso Stecconi, Antonio La Porta, Ludovico Carraria-Martinotti, Bert Jan Offrein, Valeria Bragaglia. 1-4 [doi]
• Improvement of GIDL-assisted Erase by using Surrounded BL PAD Structure for VNANDSuhwan Lim, Samki Kim, ChangHee Lee, Hyeongwon Choi, Nambin Kim, Jaehun Jung, Hanvit Yang, Tae Hun Kim, Junhee Lim, Daewon Ha, Sunghoi Hur, Jae-Hoon Jang, Yu Gyun Shin, Jaihyuk Song. 1-4 [doi]
• SLC and MLC In-Memory-Approximate-Search Solutions in Commercial 48-layer and 96-layer 3D-NAND Flash MemoriesPo-Hao Tseng, Tian-Cig Bo, Yu-Hsuan Lin, Yu-Chao Lin, Jhe-Yi Liao, Feng-Ming Lee, Yu-Yu Lin, Ming-Hsiu Lee, Kuang-Yeu Hsieh, Keh-Chung Wang, Chih-Yuan Lu. 1-4 [doi]
• Trends and Future Challenges of 3D NAND Flash MemorySun Il Shim, Jaehoon Jang, Jaihyuk Song. 1-4 [doi]
• In-memory neural network accelerator based on phase change memory (PCM) with one-selector/one-resistor (1S1R) structure operated in the subthreshold regimeNicola Lepri, P. Gibertini, Piergiulio Mannocci, A. Pirovano, I. Tortorelli, Paolo Fantini, Daniele Ielmini. 1-4 [doi]
• Ferroelectric HfO2/ZrO2 Superlattices with Improved Leakage at Bias and Temperature StressDavid Lehninger, Ayse Sünbül, Ricardo Olivo, Thomas Kämpfe, Konrad Seidel, Maximilian Lederer. 1-4 [doi]
• th Generation 1Tb Quad-Level Cell 3D NAND Flash Memory in Mass ProductionSoochan Chung, Dong-Hyeon Ko, Joonsung Lim, Kyungmoon Kim, Sejie Takaki, Yujeong Seo, Byoungil Lee, Sejun Park, Jaeduk Lee, Kyungyoon Noh, Su-Jin Ahn, Sunghoi Hur. 1-4 [doi]
• An 18nm ePCM with BJT selector NVM design for advanced microcontroller applicationsAntonino Conte, Francesco Tomaiuolo, Marco Ruta, Andrea Redaelli, Franck Arnaud, Thomas Jouanneau, Christian Boccaccio, Olivier Weber. 1-4 [doi]
• Demonstration of multilevel multiply accumulate operations for AiMC using engineered a-IGZO transistors-based 2T1C gain cell arraysSubhali Subhechha, Stefan Cosemans, Attilio Belmonte, Nouredine Rassoul, Shamin Houshmand Sharifi, Peter Debacker, Diederik Verkest, Romain Delhougne, Gouri Sankar Kar. 1-4 [doi]
• Overlay Control in HAR device integrationPradeep Subrahmanyan, Wonjae Lee, Jeff Lischer, Ram Karur, Olga Kucher, Stan Todorov, Adaeze Osonkie. 1-4 [doi]
• Stochastic Computing-based Computation-in-Memory (SC CiM) Architecture for DNNs and Hierarchical Evaluations of Non-volatile Memory Error and Defect ToleranceTakuto Nishimura, Yuya Ichikawa, Akira Goda, Naoko Misawa, Chihiro Matsui, Ken Takeuchi. 1-4 [doi]
• Spin-orbit torque MRAM for ultrafast cache and neuromorphic computing applicationsSiddharth Rao, Kaiming Cai, Giacomo Talmelli, Nathali Franchina-Vergel, Ward Janssens, Hubert Hody, Farrukh Yasin, Kurt Wostyn, Sebastien Couet. 1-4 [doi]
• Effect of High-Temperature Bake on RTN Statistics in Floating Gate Flash Memory ArraysViktor Markov, Gilles Festes, Louisa Schneider, Steven Lemke, Serguei Jourba, Alexander Kotov. 1-4 [doi]
• Benefits of Design Assist Techniques on Performances and Reliability of a RRAM MacroBastien Giraud, S. Ricavy, Yasser Moursy, C. Laffond, I. Sever, Valentin Gherman, M. Pezzin, F. Lepin, M. Diallo, K. Zenati, S. Dumas, M. Vershkov, Alessandro Bricalli, Giuseppe Piccolboni, Jean-Philippe Noël, A. Samir, Gaël Pillonnet, Yvain Thonnart, Gabriel Molas. 1-4 [doi]
• A Simulation Study of Scaling Capability toward 10nm for the 3D Stackable Gate-Controlled Thyristor (GCT) DRAM DeviceWei-Chen Chen, Hang-Ting Lue, Tzu-Hsuan Hsu, Keh-Chung Wang, Chih-Yuan Lu. 1-4 [doi]
• SONOS Embedded Flash IP Using Trap-Depth-Controlled SiN Film Enabling Data Retention more than 10 years at 200°CYasuhiro Taniguchi, Shoji Yoshida, Teruhiko Egashira, ChihBin Kuo, YiYang Shie, Yuchun Wang, Chenyu Huang, Tsuyoshi Tamatsu, Keiji Okamoto, Masanobu Hishiki, Yasushi Sasaki, Fukuo Owada, Nobuhiko Ito, Yutaka Shinagawa, ChihMing Kuo, Satoshi Noda, Toshikazu Matsui, Kosuke Okuyama. 1-4 [doi]
• Improved MW of IGZO-channel FeFET by Reading Scheme Optimization and Interfacial EngineeringZhuo Chen, Nicolo Ronchi, Amey Walke, Kaustuv Banerjee, Mihaela Ioana Popovici, Kostantine Katcko, Geert Van den bosch, Maarten Rosmeulen, Valeri Afanas'ev, Jan Van Houdt. 1-4 [doi]
• Low Power and Thermal Throttling-less SSD with In-Package Boost Converter for 1000-WL Layer 3D Flash MemoryKazuma Hasegawa, Yuta Aiba, Xu Li, Hitomi Tanaka, Takayuki Miyazaki, Hideko Mukaida, Masaru Koyanagi, Masayuki Miura, Tomoya Sanuki. 1-4 [doi]
• Optimization of Retention in Ferroelectricity Boosted Gate Stacks for 3D NANDLaurent Breuil, Mihaela Popovici, J. Stiers, Antonio Arreghini, S. Ramesh, G. Van den bosch, Jan Van Houdt, Maarten Rosmeulen. 1-4 [doi]
• Dielectric Relaxation Performance of DRAM Storage Capacitors and Ways of ImprovementZ. Asher Bai, Yixian Wang, Lixue Liu, Xi Zhang, Feng Yuan, Junsheng Meng, Zhongming Liu, Js Jeon, James Cho, Blacksmith Wu, Huihui Li, Guilei Wang, Chao Zhao, Kanyu Cao. 1-4 [doi]
• Memory Window in Si: HfO2 FeRAM arrays: Performance Improvement and Extrapolation at Advanced NodesJ. Laguerre, Marc Bocquet, Olivier Billoint, S. Martin, Jean Coignus, Catherine Carabasse, T. Magis, T. Dewolf, François Andrieu, Laurent Grenouillet. 1-4 [doi]