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Improved 3D DRAM Design Based on Gate-Controlled Thyristor Featuring Two Asymmetrical Horizontal WL's and Vertical BL for Better Cell Size Scaling and Array Selection

Wei-Chen Chen, Hang-Ting Lue, Ming-Hung Wu, Yu-Tang Lin, Keh-Chung Wang, Chih-Yuan Lu. Improved 3D DRAM Design Based on Gate-Controlled Thyristor Featuring Two Asymmetrical Horizontal WL's and Vertical BL for Better Cell Size Scaling and Array Selection. In IEEE International Memory Workshop, IMW 2024, Seoul, Republic of Korea, May 12-15, 2024. pages 1-4, IEEE, 2024. [doi]

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