First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles

Yu-Rui Chen, Yi-Chun Liu, Zefu Zhao, Wan-Hsuan Hsieh, Jia-Yang Lee, Chien-Te Tu, Bo-Wei Huang, Jer-Fu Wang, Shee-Jier Chueh, Yifan Xing, Guan-Hua Chen, Hung-Chun Chou, Dong Soo Woo, M. H. Lee, C. W. Liu. First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles. In 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023. pages 1-2, IEEE, 2023. [doi]

@inproceedings{ChenLZHLTHWCXCC23,
  title = {First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles},
  author = {Yu-Rui Chen and Yi-Chun Liu and Zefu Zhao and Wan-Hsuan Hsieh and Jia-Yang Lee and Chien-Te Tu and Bo-Wei Huang and Jer-Fu Wang and Shee-Jier Chueh and Yifan Xing and Guan-Hua Chen and Hung-Chun Chou and Dong Soo Woo and M. H. Lee and C. W. Liu},
  year = {2023},
  doi = {10.23919/VLSITechnologyandCir57934.2023.10185284},
  url = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185284},
  researchr = {https://researchr.org/publication/ChenLZHLTHWCXCC23},
  cites = {0},
  citedby = {0},
  pages = {1-2},
  booktitle = {2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023},
  publisher = {IEEE},
  isbn = {978-4-86348-806-9},
}